ramips: change CM_GCR_BASE_CMDEFTGT_MEM value to match datasheet

Zero config value for default memory region means 'memory', not
not 'disabled' according to 'Control Registers Of The Coherency
Manager' manual.

Signed-off-by: Nikolay Martynov <[email protected]>
SVN-Revision: 47906

diff --git a/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch b/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch
new file mode 100644 (file)
index 0000000..6b9e9e3
--- /dev/null
+++ b/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch
@@ -0,0 +1,12 @@
+--- a/arch/mips/include/asm/mips-cm.h
++++ b/arch/mips/include/asm/mips-cm.h
+@@ -225,8 +225,7 @@ BUILD_CM_Cx_R_(tcid_8_priority,    0x80)
+ #define CM_GCR_BASE_GCRBASE_MSK                       (_ULCAST_(0x1ffff) << 15)
+ #define CM_GCR_BASE_CMDEFTGT_SHF              0
+ #define CM_GCR_BASE_CMDEFTGT_MSK              (_ULCAST_(0x3) << 0)
+-#define  CM_GCR_BASE_CMDEFTGT_DISABLED                0
+-#define  CM_GCR_BASE_CMDEFTGT_MEM             1
++#define  CM_GCR_BASE_CMDEFTGT_MEM             0
+ #define  CM_GCR_BASE_CMDEFTGT_IOCU0           2
+ #define  CM_GCR_BASE_CMDEFTGT_IOCU1           3
+